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___Part No.___ ______ (勾選方式)	___Features___	Vcc(MIN)(V) (Range)	Vcc(MAX)(V) (Range)	___Voltage Class(V)___ ______ (勾選方式)	tD(nS) (Range)	tR(nS) (Range)	tF(nS) (Range)	___Package___ ______ (勾選方式)
___US2829___	___Single-Channel High-Speed MOSFET Driver___ ______ ___* Low-cost single-channel high-speed MOSFET driver___ ___* 2A peak output current___ ___* 25ns max rise/fall times and 40ns max propagation delay,1nF load___ ___* Low power dissipation: ICC=15μA(Max)___	4	14	___14___	40	25	25	___SOT-25___
___UTC4424___	___3A Dual High-Speed Power MOSFET Drivers___ ______ ___* Power supply voltage: 4.5V to 18V___ ___* High Capacitive Load Drive Capability: 1800pF in 25 ns___ ___* Short Delay Times: <40 ns (typ)___ ___* Low Output Impedance: 3.5Ω (Typ.)___	4.5	18	___18___	75	35	35	___DIP-16___ ___SOP-16___
___UGD9511___	___SINGLE-CHANNEL___ ___,HIGH-SPEED, LOW-SIDE GATE___ ___DRIVER___ ______ ___* Low-Cost Gate-Driver Device Offering Superior___ ___Replacement of NPN and PNP Discrete Solutions___ ___* Strong Sink Current Offers Enhanced Immunity against___ ___Miller Turn on___ ___* Split Output Configuration (Allows Easy and___ ___Independent Adjustment of Turn on and Turn off___ ___Speeds) in the UGD9511 Saves 1 Diode___ ___* Fast Propagation Delays (13-nsTypical)___ ___* Fast Rise and Fall Times (9ns and 7ns Typical)___ ___* 4.5V to 18V Single Supply Range___ ___* Output Held Low When Input Pins Are Floating___ ___* Outputs Held Low During VDD UVLO (Ensures___ ___Glitch-Free Operation at Power Up and Power-Down)___ ___* TTL and CMOS Compatible Input-Logic Threshold___ ___(Independent of Supply Voltage)___ ___* Hysteretic-Logic Thresholds for High-Noise Immunity___ ___* Dual-Input Design (Choice of an Inverting (IN–Pin) or___ ___Non inverting (IN+ Pin) Driver Configuration)___ ___Unused Input Pin can be Used for Enable or Disable___ ___Function___ ___* Input Pin Absolute Maximum Voltage Levels___	4.5	18	___18___	30	22	11	___SOT-26___
___UTR2101___	___HALF-BRIDGE DRIVER___ ______ ___* Floating channel designed for bootstrap operation___ ___* Fully operational to +600V___ ___* Tolerant to negative transient voltage, dV/dt immune___ ___* Gate drive supply range from 10V to 20V___ ___* Undervoltage lockout___ ___* 3.3V, 5V, and 15V input logic compatible___ ___* Matched propagation delay for both channels___ ___* Outputs in phase with inputs___	10	20	___600___	-	90	90	___SOP-8___
___UTR2103___	___HALF-BRIDGE DRIVER___ ______ ___* Floating channel designed for bootstrap operation___ ___* Fully operational to 600V___ ___* Tolerant to negative transient voltage, dV/dt immune___ ___* Gate drive supply range from 10V to 20V___ ___* Undervoltage lockout___ ___* 3.3V, 5V, and 15V input logic compatible___ ___* Cross-conduction prevention logic___ ___* Internally set deadtime___ ___* High-side output in phase with HIN input___ ___* Low-side output out of phase with LIN input___ ___* Shutdown input turns off both channels___ ___* Matched propagation delay for both channels___	10	20	___600___	850	170	90	___SOP-8___ ___DIP-8___
___UTR2104___	___HALF-BRODGE DRIVER___ ______ ___* Floating channel designed for bootstrap operation___ ___* Fully operational to 600V___ ___* Tolerant to negative transient voltage, dV/dt immune___ ___* Gate drive supply range from 10V to 20V___ ___* Undervoltage lockout___ ___* 3.3V, 5V, and 15V input logic compatible___ ___* Cross-conduction prevention logic___ ___*Internally set deadtime___ ___*High-side output in phase with input___ ___* Shutdown input turns off both channels___ ___* Matched propagation delay for both channels___	10	20	___600___	60	170	90	___SOP-8___
___UTR2011___	___HIGH AND LOW SIDE___ ___DRIVER___ ______ ___*Floating channel designed for bootstrap operation___ ___*Fully operational to 200V___ ___*Tolerant to negative transient voltage, dV/dt immune___ ___*Gate drive supply range from 10V to 20V___ ___*Independent low and high side channels___ ___*Input logic HIN/LIN active high___ ___*Undervoltage lockout for both channels___ ___*3.3V and 5V logic compatible___ ___*CMOS Schmitt-triggered inputs with pull-down___ ___*Matched propagation delay for both channels___	10	20	___200___	-	40	35	___SOP-8___
___UTR2117___	___HIGH SIDE DRIVER___ ______ ___* Floating channel designed for bootstrap operation___ ___* Fully operational to 600V___ ___* Tolerant to negative transient voltage, dV/dt immune___ ___* Gate drive supply range from 10V to 20V___ ___* Undervoltage lockout___ ___* CMOS Schmitt-triggered inputs with pull-down___ ___* Output in phase with input___	10	20	___600___	-	130	65	___SOP-8___ ___DIP-8___
___UTR2304___	___HALF-BRIDGE DRIVER___ ______ ___* Floating channel designed for bootstrap operation___ ___* Fully operational to 600V___ ___* Tolerant to negative transient voltage, dV/dt immune___ ___* Gate drive supply range from 10V to 20V___ ___* Undervoltage lockout___ ___* 3.3V, 5V, and 15V input logic compatible___ ___* Cross-conduction prevention logic___ ___* Matched propagation delay for both channels___ ___* Internal 100 ns deadtime___ ___* Outputs in phase with inputs___ ___* RoHS compliant___	10	20	___600___	190	120	60	___SOP-8___
___UTR2113___	___HIGH AND LOW SIDE DRIVER___ ______ ___* Floating channel designed for bootstrap operation___ ___* Fully operational to 600V___ ___* Tolerant to negative transient voltage, dV/dt immune___ ___* Gate drive supply range from 10V to 20V___ ___* Undervoltage lockout for both channels___ ___* 3.3V logic compatible___ ___* Separate logic supply range from 3.3V to 20V___ ___* Logic and power ground ± 5V offset___ ___* CMOS Schmitt-triggered inputs with pull-down___ ___* Cycle by cycle edge-triggered shutdown logic___ ___* Matched propagation delay for both channels___ ___* Outputs in phase with inputs___	10	20	___600___	-	35	25	___DIP-16___
___UC1010___	___IGNITION GATE DRIVER IC___ ______ ___* Signal Line Input Buffer___ ___* Ground shift tolerance ±1.5 V___ ___* Input spike filter___ ___* Programmable maximum dwell time___ ___* Programmable Input Pull down current___ ___* Operation from Ignition or Battery line___ ___* Control IGBT current limiting through Vsense pin___ ___* Soft Shutdown following Max Dwell Time out___	4	28	___6.5___	15	-	-	___SOT-25___